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cy7c1327g 4-mbit (256 k 18) pipelined sync sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05519 rev. *o revised october 8, 2013 4-mbit (256 k 18) pipelined sync sram features registered inputs and outputs for pipelined operation 256 k 18 common i/o architecture 3.3 v core power supply (v dd ) 2.5 v i/o power supply (v ddq ) fast clock-to -output times ? 3.5 ns (for 166-mhz device) provide high performance 3-1-1-1 access rate user-selectable burst counter supporting intel ? ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed writes asynchronous output enable offered in pb-free 100-pin tqfp package ?zz? sleep mode option functional description the cy7c1327g sram integrates 256 k 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw [a:b] , and bwe), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self-tim ed write cycle.this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to two bytes wi de as controlled by the byte write control inputs. gw when active low causes all bytes to be written. the cy7c1327g operates from a +3.3 v core power supply while all outputs also operate with a +3.3 v or a +2.5 v supply. all inputs and outputs are jedec-standard jesd8-5- compatible. a 0, a1, a address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b write register dq a, dqp a write register enable register oe sense amps memory array adsp 2 mode ce2 ce3 gw bwe pipelined enable dqs dqp a dqp b output registers input registers e dq a, dqp a write driver output buffers dq b, dqp b write driver a[1:0] zz sleep control logic block diagram errata: for information on silicon errata, see "errata" on page 21. details include trigger conditions, devices affected, and proposed workaround.
cy7c1327g document number: 38-05519 rev. *o page 2 of 24 contents selection guide ................................................................ 3 pin configurations ........................................................... 3 pin definitions .................................................................. 4 functional overview ........................................................ 6 single read accesses ................................................ 6 single write accesses initia ted by adsp ................... 6 single write accesses initiate d by adsc ................... 6 burst sequences ......................................................... 6 sleep mode ................................................................. 6 interleaved burst address tabl e ................................. 7 linear burst address table ......................................... 7 zz mode electrical characteri stics .............................. 7 truth table ........................................................................ 8 truth table for read/write .............................................. 9 maximum ratings ........................................................... 10 operating range ............................................................. 10 neutron soft error immunity ......................................... 10 electrical characteristics ............................................... 10 capacitance .................................................................... 11 thermal resistance ........................................................ 11 ac test loads and waveforms ..................................... 12 switching characteristics .............................................. 13 switching waveforms .................................................... 14 ordering information ...................................................... 18 ordering code definitions ..... .................................... 18 package diagrams .......................................................... 19 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 errata ............................................................................... 21 part numbers affected .............................................. 21 product status ........................................................... 21 ram9 sync zz pin issues errata summary .............. 21 document history page ................................................. 22 sales, solutions, and legal information ...................... 24 worldwide sales and design s upport ......... .............. 24 products .................................................................... 24 psoc? solutions ...................................................... 24 cypress developer community ................................. 24 technical support ................. .................................... 24
cy7c1327g document number: 38-05519 rev. *o page 3 of 24 selection guide description 166 mhz 133 mhz unit maximum access time 3.5 4.0 ns maximum operating current 240 225 ma maximum cmos standby current 40 40 ma pin configurations figure 1. 100-pin tqfp pinout [1] a a a a a 1 a 0 nc/72m nc/36m v ss v dd nc/18m nc/9m a a a a a a a a nc nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode byte a byte b cy7c1327g note 1. errata: the zz pin (pin 64) needs to be externally connected to ground. for more information, see "errata" on page 21.
cy7c1327g document number: 38-05519 rev. *o page 4 of 24 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the 256 k address locations. sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1, a0 feed the 2-bit counter. bw a , bw b input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw [a:b] and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselec t the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/desel ect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tristated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk , active low . when asserted, it automatically incr ements the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, a is captured in the addre ss registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. zz [2] input- asynchronous zz ?sleep? input, active high . this input, when high places the device in a non-time-critical ?sleep? condition with data integrity preserved. during normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. note 2. errata: the zz pin (pin 64) needs to be externally connected to ground. for more information, see "errata" on page 21.
cy7c1327g document number: 38-05519 rev. *o page 5 of 24 adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, a is captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. dq a, dq b , dqp a, dqp b i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, t hey deliver the data contained in the memory location specified by ?a? during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp [a:b] are placed in a tristate condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq i/o ground ground for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. nc, nc/9m, nc/18m, nc/72m, nc/144m, nc/288m, nc/576m, nc/1g ? no connects . not internally connected to the di e. nc/9m, nc/18m, nc/ 72m, nc/144m, nc/288m, nc/576m and nc/1g are address expansion pins are not internally connected to the die. pin definitions (continued) name i/o description
cy7c1327g document number: 38-05519 rev. *o page 6 of 24 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. the cy7c1327g supports seconda ry cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for proces sors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw [a:b] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous ch ip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tristate control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address advancement logic and the address register while being presented to the memory array. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within t co if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always trista ted during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. once the sram is des elected at clock rise by the chip select and either adsp or adsc signals, its output will tristate immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) ad sp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the write signals (gw , bwe , and bw [a:b] ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dq inputs is written into the corresponding address location in the memory array. if gw is high, then the write operation is controlled by bwe and bw [a:b] signals. the cy7c1327g provides byte write capability that is described in the write cycle descriptions tabl e. asserting the byte write enable input (bwe ) with the selected byte write (bw [a:b] ) input, will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1327g is a common i/o device, the output enable (oe ) must be deserted high before presenting data to the dq inputs. doing so will tristate the output drivers. as a safety precaution, dqs are automatica lly tristated whenever a write cycle is detected, regardle ss of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw [a:b] ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address pres ented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the adv input is ignored during this cycle. if a global write is conducted, the da ta presented to dq is written into the corresponding address location in the memory core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronou s self-timed write mechanism has been provided to simplify the write operations. because the cy7c1327g is a common i/o device, the output enable (oe ) must be deserted high before presenting data to the dq inputs. doing so will tristate the output drivers. as a safety precaution, dqs are automatica lly tristated whenever a write cycle is detected, regardle ss of the state of oe . burst sequences the cy7c1327g provides a two- bit wraparound counter, fed by a1:a0, that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data inte grity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low.
cy7c1327g document number: 38-05519 rev. *o page 7 of 24 interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz snooze mode standby current zz > v dd ? ? 0.2 v ? 40 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to snooze current this parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit snooze curre nt this parameter is sampled 0 ? ns
cy7c1327g document number: 38-05519 rev. *o page 8 of 24 truth table the truth table for cy7c1327g follows. [3, 4, 5, 6, 7] next cycle add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power-down none h x x l x l x x x l?h tristate deselect cycle, power-down none l l x l l x x x x l?h tristate deselect cycle, power-down none l x h l l x x x x l?h tristate deselect cycle, power-down none l l x l h l x x x l?h tristate deselect cycle, power-down none l x h l h l x x x l?h tristate snooze mode, power-down none x x x h x x x x x x tristate read cycle, begin burst external l h l l l x x x l l?h q read cycle, begin burst external l h l l l x x x h l?h tristate write cycle, begin burst external l h l l h l x l x l?h d read cycle, begin burst external l h l l h l x h l l?h q read cycle, begin burst external l h l l h l x h h l?h tristate read cycle, continue burst next x x x l h h l h h l?h tristate read cycle, continue burst next x x x l h h l h l l?h q read cycle, continue burst next h x x l x h l h l l?h q read cycle, continue burst next h x x l x h l h h l?h tristate write cycle, continue burst next x x x l h h l l x l?h d write cycle, continue burst next h x x l x h l l x l?h d read cycle, suspend burst current x x x l h h h h l l?h q read cycle, suspend burst current x x x l h h h h h l?h tristate read cycle, suspend burst current h x x l x h h h l l?h q read cycle, suspend burst current h x x l x h h h h l?h tristate write cycle, suspend burst current x x x l h h h l x l?h d write cycle, suspend burst current h x x l x h h l x l?h d notes 3. x = ?don't care.? h = logic high, l = logic low. 4. write = l when any one or more byte write enable signals (bw a , bw b ) and bwe = l or gw = l. write = h when all byte write enable signals (bw a , bw b ), bwe , gw = h. 5. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw [a: b] . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tristate. oe is a don't care for the remainder of the write cycle. 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tristate when oe is inactive or when the device is deselected, and a ll data bits behave as output when oe is active (low).
cy7c1327g document number: 38-05519 rev. *o page 9 of 24 truth table for read/write the truth table for read/write follows. [8] function gw bwe bw b bw a read hhxx read hlhh write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write bytes b, a h l l l write all bytes h l l l write all bytes l x x x note 8. x = ?don't care.? h = logic high, l = logic low.
cy7c1327g document number: 38-05519 rev. *o page 10 of 24 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v dd relative to gnd .......?0.5 v to +4.6 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc voltage applied to outputs in tristate ...........................................?0.5 v to v ddq + 0.5 v dc input voltage .............. .............. ..... ?0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) .......................... > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 ? c to +70 ? c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 ? c to +85 ? c neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 361 394 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch-up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculat ion. for more details refer to application note an54908 ?accelerated neutron ser testing and calculation of terrestrial failure rates?. electrical characteristics over the operating range parameter [9, 10] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [9.] for 3.3 v i/o 2.0 v dd + 0.3 v v for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [9.] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a notes 9. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 10. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1327g document number: 38-05519 rev. *o page 11 of 24 i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 6 ns cycle, 166 mhz ?240ma 7.5 ns cycle, 133 mhz ?225ma i sb1 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc 6 ns cycle, 166 mhz ?100ma 7.5 ns cycle, 133 mhz ?90ma i sb2 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = 0 all speeds ? 40 ma i sb3 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc 6 ns cycle, 166 mhz ?85ma 7.5 ns cycle, 133 mhz ?75ma i sb4 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 all speeds ? 45 ma electrical characteristics (continued) over the operating range parameter [9, 10] description test conditions min max unit capacitance parameter [11] description test conditions 100-pin tqfp max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 3.3 v 5pf c clk clock input capacitance 5pf c i/o input/output capacitance 5pf thermal resistance parameter [11] description test conditions 100-pin tqfp package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 30.32 c/w ? jc thermal resistance (junction to case) 6.85 c/w note 11. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1327g document number: 38-05519 rev. *o page 12 of 24 ac test loads and waveforms figure 2. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load
cy7c1327g document number: 38-05519 rev. *o page 13 of 24 switching characteristics over the operating range parameter [12, 13] description -166 -133 unit min max min max t power v dd (typical) to the first access [14] 1 ? 1 ? ms clock t cyc clock cycle time 6.0 ? 7.5 ? ns t ch clock high 2.5 ? 3.0 ? ns t cl clock low 2.5 ? 3.0 ? ns output times t co data output valid after clk rise ? 3.5 ? 4.0 ns t doh data output hold after clk rise 1.5 ? 1.5 ? ns t clz clock to low z [15, 16, 17] 0 ? 0 ? ns t chz clock to high z [15, 16, 17] ? 3.5 ? 4.0 ns t oev oe low to output valid ? 3.5 ? 4.5 ns t oelz oe low to output low z [15, 16, 17] 0 ? 0 ? ns t oehz oe high to output high z [15, 16, 17] ? 3.5 ? 4.0 ns set-up times t as address set-up before clk rise 1.5 ? 1.5 ? ns t ads adsc , adsp setup before clk rise 1.5 ? 1.5 ? ns t advs adv setup before clk rise 1.5 ? 1.5 ? ns t wes gw , bwe , bw x setup before clk rise 1.5 ? 1.5 ? ns t ds data input setup before clk rise 1.5 ? 1.5 ? ns t ces chip enable setup before clk rise 1.5 ? 1.5 ? ns hold times t ah address hold after clk rise 0.5 ? 0.5 ? ns t adh adsp , adsc hold after clk rise 0.5 ? 0.5 ? ns t advh adv hold after clk rise 0.5 ? 0.5 ? ns t weh gw , bwe , bw x hold after clk rise 0.5 ? 0.5 ? ns t dh data input hold after clk rise 0.5 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.5 ? 0.5 ? ns notes 12. timing references level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v on all data sheets. 13. test conditions shown in (a) of figure 2 on page 12 unless otherwise noted. 14. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 15. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 2 on page 12 . transition is measured 200 mv from steady-state voltage. 16. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect paramete rs guaranteed over worst case user condi tions. device is designed to achieve high z prior to low z under the same system conditions. 17. this parameter is sampled and not 100% tested.
cy7c1327g document number: 38-05519 rev. *o page 14 of 24 switching waveforms figure 3. read cycle timing [18] t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bw [a:b] d ata out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address dont care undefined note 18. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high.
cy7c1327g document number: 38-05519 rev. *o page 15 of 24 figure 4. write cycle timing [19, 20] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw[a :b] d ata out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined notes 19. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 20. full width write can be initiated by either gw low; or by gw high, bwe low and bw [a:b] low.
cy7c1327g document number: 38-05519 rev. *o page 16 of 24 figure 5. read/write cycle timing [21, 22, 23] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw [a:b] d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 dont care undefined a3 notes 21. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 22. the data bus (q) remains in high z following a writ e cycle, unless a ne w read access is initiated by adsp or adsc . 23. gw is high.
cy7c1327g document number: 38-05519 rev. *o page 17 of 24 figure 6. zz mode timing [24, 25] switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 24. device must be deselected when entering zz mode. see cycle desc riptions table for all possible signal conditions to deselect the device. 25. dqs are in high z when exiting zz sleep mode.
cy7c1327g document number: 38-05519 rev. *o page 18 of 24 ordering code definitions ordering information the table below contains only the parts that are currently availa ble. if you don?t see what you are looking for, please contact your local sales representative. for more info rmation, visit the cypress website at www.cypress.com and refer to th e product summary page at http://www.cypress.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representat ives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/go/datasheet/offices speed (mhz) ordering code package diagram package type operating range 133 cy7c1327g-133axi 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free industrial 166 cy7c1327g-166axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial temperature range: x = c or i c = commercial; i = industrial pb-free package type: a = 100-pin tqfp speed grade: xxx = 133 mhz or 166 mhz process technology: g ? 90 nm 1327 = scd, 256 k 18 (4 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c 1327 g - xxx x a cy 7 x
cy7c1327g document number: 38-05519 rev. *o page 19 of 24 package diagrams figure 7. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1327g document number: 38-05519 rev. *o page 20 of 24 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance i/o input/output jedec joint electron devices engineering council lmbu logical multi-bit upsets lsbu logical single-bit upsets oe output enable sel single event latch-up sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere ms millisecond mm millimeter mv millivolt nm nanometer ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1327g document number: 38-05519 rev. *o page 21 of 24 errata this section describes the ram9 sync zz pin issue. details incl ude trigger conditions, the devices affected, proposed workaroun d and silicon revision applicability. please contact your local cypress sales representative if you have further questions. part numbers affected product status all of the devices in the ram9 4mb sync family are qualified and availabl e in production quantities. ram9 sync zz pin issues errata summary the following table defines the errata applicable to available ram9 4mb sync family devices. 1. zz pin issue problem definition the problem occurs only when the device is operated in the no rmal mode with zz pin left floating. the zz pin on the sram device does not have an internal pull-do wn resistor. switching noise in the system may cause the sram to recognize a high on the zz input, which may cause the sram to enter sleep mode. this could result in incorrect or undesirable operation of the sram. trigger conditions device operated with zz pin left floating. scope of impact when the zz pin is left floating, the device delivers incorrect data. workaround tie the zz pin externally to ground. fix status for the 4m ram9 (90 nm) devices, there is no plan to fix this issue. density & revision package type operating range 4mb-ram9 synchronous srams: cy7c132*g 100-pin tqfp commercial/ industrial item issues description device fix status 1. zz pin when asserted high, the zz pin places device in a ?sleep? condition with data integrity preserved.the zz pin currently does not have an internal pull-down resistor and hence cannot be left floating externally by the user during normal mode of operation. 4m-ram9 (90nm) for the 4m ram9 (90 nm) devices, there is no plan to fix this issue.
cy7c1327g document number: 38-05519 rev. *o page 22 of 24 document history page document title: cy7c1327g, 4-mbit (256 k 18) pipelined sync sram document number: 38-05519 rev. ecn no. submission date orig. of change description of change ** 224367 see ecn rkf new data sheet. *a 278513 see ecn vbl updated ordering information (updated part numbers (changed tqfp to pb-free tqfp, added pb-free bga packages)). *b 332895 see ecn syt updated features (removed 225 mhz, 100 mhz frequencies related information). updated selection guide (removed 225 mhz, 100 mhz frequencies related information). updated pin configurations (modified address expansion balls in the pinouts for 100-pin tqfp and 119-ball bga packages as per jedec standards). updated pin definitions . updated electrical characteristics (removed 225 mhz, 100 mhz frequencies related information, updated test conditions of v ol and v oh parameters). updated thermal resistance (replaced values of ? ja and ? jc parameters from tbd to respective thermal values for all packages). updated switching characteristics (removed 225 mhz, 100 mhz frequencies related information). updated ordering information (by shading and unshading mpns as per availability, removed comment on the av ailability of bga lead-free package). *c 351194 see ecn pci updated ordering information (updated part numbers). *d 366728 see ecn pci updated electrical characteristics (added test conditions for v dd and v ddq parameters, updated note 10 (replaced v ih < v dd with v ih < v dd )). *e 419256 see ecn rxu changed status from preliminary to final. changed address of cypress semicondu ctor corporation from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (changed ?input load current except zz and mode? to ?input leakage current except zz and mode? in the description of i x parameter). updated ordering information (updated part numbers, replaced package name column with package diagram in the ordering information table). updated package diagrams (spec 51-85050 (changed revision from *a to *b)). *f 480124 see ecn vkn updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers). *g 2756340 08/26/2009 vkn/aesa added neutron soft error immunity . updated ordering information (by including parts that are available, and modified the disclaimer for the ordering information). *h 3044512 10/01/2010 njy added ordering code definitions . updated package diagrams . added acronyms and units of measure . minor edits and updated in new template. *i 3363203 09/05/2011 prit updated package diagrams . updated in new template.
cy7c1327g document number: 38-05519 rev. *o page 23 of 24 *j 3612268 05/09/2012 prit updated features (removed 250 mhz, 200 mhz frequencies related information, removed 119-ball bga package related information). updated functional description (removed the note ?for best practices recommendations, refer to the cypress application note system design guidelines on www.cypress.com .? and its reference). updated selection guide (removed 250 mhz, 200 mhz frequencies related information). updated pin configurations (removed 119-ball bga package related information). updated electrical characteristics (removed 250 mhz, 200 mhz frequencies related information). updated capacitance (removed 119-ball bga package related information). updated thermal resistance (removed 119-ball bga package related information). updated switching characteristics (removed 250 mhz, 200 mhz frequencies related information). *k 3749841 09/20/2012 prit no technical updates. completing sunset review. *l 3984870 05/02/2013 prit added errata . *m 4039228 06/25/2013 prit added erra ta footnotes (note 1, 2). updated pin configurations : added note 1 and referred the same note in figure 1 . updated pin definitions : added note 2 and referred the same note in zz pin. updated in new template. *n 4077099 07/25/2013 prit updated truth table . *o 4150660 10/08/2013 prit updated errata . document history page (continued) document title: cy7c1327g, 4-mbit (256 k 18) pipelined sync sram document number: 38-05519 rev. ecn no. submission date orig. of change description of change
document number: 38-05519 rev. *o revised october 8, 2013 page 24 of 24 i486 is a trademark, and intel and pentium are registered trademarks, of intel corporation. powerpc is a registered trademark o f ibm corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1327g ? cypress semiconductor corporation, 2004-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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